When the pulse width of pulse signals has to be adjusted by extending or shortening the pulse width, a circuit configuration is used in which the pulse width is extended or shortened using a logic gate. In a circuit configuration using a logic gate, a delay occurs in the leading edge of pulse signals whose pulse width has been adjusted.
One example of a pulse width delaying circuit of the prior art is shown in FIG. 1. This pulse width delaying circuit 100 has a pulse delaying circuit 110 and an OR gate 120. The pulse width delaying circuit 110 is an even number of two or more inverters, NOT circuits, connected in series. The OR gate 120 is an inverter connected in series to a two-input NOR (negated OR) circuit. The pulse delaying circuit 110 generates a delayed pulse signal b from the inputted pulse signal a, the OR gate 120 generates a logical sum of inputted pulse signal a and delayed pulse signal b, and an outputted pulse signal c with an extended pulse width is generated.
One example of a pulse width shortening circuit of the prior art is shown in FIG. 2. This pulse width shortening circuit 200 is composed of a pulse delaying circuit 210 and an AND gate 220. The pulse delaying circuit 210 is an odd number of inverters connected in series. The AND gate 220 is an inverter connected in series to a two-input NAND (negated AND) circuit. The pulse delaying circuit 210 generates a delayed pulse signal b from the inputted pulse signal a, the AND gate 220 generates a logical product of the inputted pulse signal a and the delayed pulse signal b, and an outputted pulse signal c with a shortened pulse width is generated.
Because the pulse width extending circuit 100 and the pulse width shortening circuit 200 are circuit configurations using, respectively, an OR gate 120 and an AND gate 220, a delay occurs at the leading edge of an outputted pulse signal c whose pulse width has been adjusted, and this delay has to be minimized in circuit designs requiring precise timing.
A signal change detecting circuit for generating a pulse signal with a predetermined pulse width is disclosed in JP Patent No. 3,903,588, in which a transfer gate and a fuse circuit for controlling the ON/OFF state of the transfer gate are provided.
A pulse width extending circuit is disclosed in JP Patent No. 3,444,975, in which a logical sum of an inputted pulse signal and extended pulse signal of this is generated, and the pulse width is extended.
A pulse width varying circuit is disclosed in Japanese Laid-open Patent Publication No. 10-242817, in which the circuit has a transfer gate through which an inputted pulse signal passes, and in which the transfer gate is controlled by a control signal not based on the inputted pulse signal.
A pulse width extending circuit is disclosed in Japanese Laid-open Patent Publication No. 2001-223569, in which a plurality of buffers are connected in series in three steps, the buffers are connected in series via AND gates between each step, an OR operation is performed on the input signal at the final third-step input end, the output signals of each step, and the output signal at the final third-step output end, and the pulse width is extended.